`include "include.v"

module inst_mem #( parameter AWIDTH = 7,
                             DWIDTH = 16)
(
  input  wire                clka,
  input  wire  [AWIDTH-1:0]  addra,
  output reg   [DWIDTH-1:0]  douta
);

parameter DEPTH = (1 << AWIDTH);

reg [DWIDTH-1:0] imem [0:DEPTH-1];

always @(posedge clka) begin
  douta <= imem[addra];
end

endmodule
